| CPC G11C 7/222 (2013.01) [G11C 7/109 (2013.01); G11C 7/1048 (2013.01); G11C 7/1063 (2013.01)] | 6 Claims |
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1. A memory controller configured to access a memory including a plurality of banks, comprising:
a holding circuit configured to hold a plurality of read or write access requests from a bus master;
a read/write control circuit configured to select one of the access requests held in the holding circuit and issue a read command or a write command; and
an active control circuit configured to select the access request held in the holding circuit and issue an active command,
wherein the active control circuit includes
a generation circuit that generates number of activated read commands and number of activated write commands, the number of activated read commands is the total number of read commands of an access for which the active command is issued among the access requests held in the holding circuit, and the number of activated write commands is the total number of the write commands of an access for which the active command is issued among the access requests held in the holding circuit, and
a selection circuit that, when the number of activated read commands is equal to or more than a first threshold, preferentially issues the active command of an read access in which the number obtained by adding the number of read commands of each of the read accesses requiring issue of the active command among the accesses held in the holding circuit and the number of activated read commands is equal to or more than a second threshold and,
when the number of activated write commands is equal to or more than the first threshold, preferentially issues the active command of a write access in which the number obtained by adding the number of write commands of each of the write accesses requiring the issue of the active command among the accesses held in the holding circuit and the number of activated write commands is equal to or more than the second threshold.
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