US 11,694,732 B2
Active random access memory
Hsin-Cheng Chen, Hsinchu (TW); Jung-Rung Jiang, Tao-Yuan (TW); and Yen-Hao Huang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 2, 2022, as Appl. No. 17/734,160.
Application 17/734,160 is a continuation of application No. 17/117,261, filed on Dec. 10, 2020, granted, now 11,322,185.
Application 17/117,261 is a continuation of application No. 15/341,372, filed on Nov. 2, 2016, granted, now 10,867,642.
Claims priority of provisional application 62/337,421, filed on May 17, 2016.
Prior Publication US 2022/0254392 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 11/418 (2006.01); G06F 12/00 (2006.01); G11C 11/419 (2006.01); G06F 12/02 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1072 (2013.01) [G06F 12/0215 (2013.01); G11C 7/1018 (2013.01); G11C 7/222 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G06F 2212/1016 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2281 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a series of commands;
determining whether the series of commands matches a pattern based on at least a current command and a prior command in the series of commands, wherein the series of commands matches the pattern when a portion of an address of the current command matches the same portion of an address of the prior command; and
asserting a ready signal upon determining that the series of commands matches the pattern,
wherein, when the ready signal is asserted, a random access memory is configured to receive and begin processing a next command upon processing the current command at a first rate instead of waiting until the current command is processed at a second, slower rate.