| CPC G09G 3/3266 (2013.01) [G09G 2300/043 (2013.01)] | 25 Claims |
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1. A gate driver including a plurality of gate stages, each of the plurality of gate stages comprising:
a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and the first carry signal synchronized with a pulse of one of the first clock signal and the second clock signal; and
a scan generating circuit outputting a scan signal having a phase which differs from phases of the first carry signal and the second carry signal, on the basis of the first clock signal, the second clock signal, and the first carry signal,
wherein each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal is a P-type pulse where a voltage of a pulse interval is lower than a voltage of a non-pulse interval, and
the scan signal is an N-type pulse where the voltage of the pulse interval is higher than the voltage of the non-pulse interval.
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