US 11,694,601 B2
Active control of light emitting diodes and light emitting diode displays
Christopher P. Hussell, Cary, NC (US)
Assigned to CreeLED, Inc., Durham, NC (US)
Filed by CreeLED, Inc., Durham, NC (US)
Filed on Mar. 11, 2020, as Appl. No. 16/815,101.
Application 16/815,101 is a continuation in part of application No. 16/542,923, filed on Aug. 16, 2019.
Application 16/542,923 is a continuation in part of application No. 16/543,009, filed on Aug. 16, 2019.
Application 16/543,009 is a continuation in part of application No. 16/437,878, filed on Jun. 11, 2019.
Application 16/437,878 is a continuation in part of application No. 16/437,878, filed on Jun. 11, 2019.
Application 16/437,878 is a continuation in part of application No. 16/369,003, filed on Mar. 29, 2019.
Prior Publication US 2020/0312231 A1, Oct. 1, 2020
Int. Cl. G09G 3/32 (2016.01); H05B 45/325 (2020.01)
CPC G09G 3/32 (2013.01) [H05B 45/325 (2020.01); G09G 2310/0275 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method of controlling a light emitting diode (LED) device, the method comprising:
providing a plurality of LED packages, each LED package of the plurality of LED packages comprising one or more LED chips and an active electrical element with a pulse width modulation (PWM) driver;
providing a PWM signal from the PWM driver to the one or more LED chips of each LED package, the PWM signal comprising a PWM period and a PWM duty cycle that corresponds to a portion of the PWM period in which the one or more LED chips are electrically activated; and
receiving an input at the active electrical element for selecting between a numerically ordered counter sequence and a non-numerically ordered counter sequence for each PWM period of each LED package;
wherein selecting the non-numerically ordered counter sequence comprising separately segmenting the PWM duty cycle within the active electrical element of each LED package such that the one or more LED chips of each LED package are electrically activated and electrically deactivated a plurality of times within the PWM period by transforming a sequential binary counter signal into the non-numerically ordered counter sequence for the PWM period by bit reversal, wherein the bit reversal comprises reversing an order of values within a sequential binary counter value to provide a modified binary counter value of the sequential binary counter signal while maintaining a bit depth of the PWM signal.