CPC G06N 3/08 (2013.01) [G06F 13/1673 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01)] | 9 Claims |
1. An integrated circuit included in a device for performing a neural network operation, the integrated circuit comprising:
a buffer configured to store feature map data in units of cells each comprising at least one feature, each of the at least one feature of each cell corresponding to a coordinate value, wherein the feature map data is for use in the neural network operation; and
a multiplexing circuit including at least one multiplexer, the multiplexing circuit being configured to
receive the feature map data from the buffer,
extract feature data from each cell, the at least one multiplexer being configured to extract each of the at least one feature of each cell corresponding to an identical coordinate value, and
output the extracted feature data.
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