US 11,694,070 B2
Bipolar all-memristor circuit for in-memory computing
Jose Cruz-Albrecht, Oak Park, CA (US); and Wei Yi, Moorpark, CA (US)
Assigned to HRL LABORATORIES, LLC, Malibu, CA (US)
Filed by HRL Laboratories, LLC, Malibu, CA (US)
Filed on Mar. 3, 2020, as Appl. No. 16/808,227.
Claims priority of provisional application 62/860,915, filed on Jun. 13, 2019.
Claims priority of provisional application 62/844,611, filed on May 7, 2019.
Prior Publication US 2020/0356344 A1, Nov. 12, 2020
Int. Cl. G06N 3/065 (2023.01); G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06F 17/15 (2006.01); G11C 11/34 (2006.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01)
CPC G06N 3/065 (2023.01) [G06F 7/5443 (2013.01); G06F 17/15 (2013.01); G06F 17/16 (2013.01); G11C 11/34 (2013.01); G11C 11/54 (2013.01); G11C 13/0002 (2013.01); H10B 63/80 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A circuit for performing energy-efficient and high throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations comprising:
a two-dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input;
an excitatory memristor neuron circuit (53) having an input coupled to a respective row input;
an inhibitory memristor neuron circuit (54) having an input coupled to the respective row input inverted;
wherein each column circuit coupled to said respective row input comprises:
a first synapse circuit (gexc) coupled to an output of the excitatory memristor neuron circuit (53) coupled to said respective row input, the first synapse circuit (gexc) having a first output;
and
a second synapse circuit (ginh) coupled to an output of the inhibitory memristor neuron circuit (54) coupled to said respective row input, the second synapse circuit (ginh) having a second output; and
an output excitatory memristor neuron circuit (57) being coupled to the first output and the second output of each column circuit, the output excitatory memristor neuron circuit (57) having an output; wherein
each memristor neuron circuit is provided for generating an output spike of constant amplitude and shape in response to any input signal sufficient for triggering the memristor neuron circuit.