US 11,694,016 B2
Fast topology bus router for interconnect planning
Zhengtao Yu, Mountain View, CA (US); Balkrishna Rashingkar, Mountain View, CA (US); David Peart, Mountain View, CA (US); Douglas Chang, Mountain View, CA (US); and Yiding Han, Mountain View, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 11, 2021, as Appl. No. 17/345,878.
Claims priority of provisional application 63/038,622, filed on Jun. 12, 2020.
Prior Publication US 2021/0390241 A1, Dec. 16, 2021
Int. Cl. G06F 30/394 (2020.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/394 (2020.01) [G06F 30/392 (2020.01); G06F 2119/18 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a netlist for a chip comprising a bus;
determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by a process comprising comparing a first demand of a first portion of the bus to a capacity of a first cell of the routing region and comparing a second demand of a second portion of the bus to a capacity of a second cell of the routing region, wherein the first cell is adjacent to the second cell in the routing region; and
generating a layout for the chip based on the first routing topology.