US 11,694,013 B2
Integrated circuit and method of manufacturing same
Ting-Wei Chiang, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); and Li-Chun Tien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 8, 2022, as Appl. No. 17/860,985.
Application 17/860,985 is a continuation of application No. 17/140,368, filed on Jan. 4, 2021, granted, now 11,409,938.
Application 17/140,368 is a continuation of application No. 16/397,064, filed on Apr. 29, 2019, granted, now 10,885,254, issued on Jan. 5, 2021.
Application 16/397,064 is a continuation of application No. 15/707,469, filed on Sep. 18, 2017, granted, now 10,296,694, issued on May 21, 2019.
Application 15/707,469 is a continuation of application No. 14/464,407, filed on Aug. 20, 2014, granted, now 9,767,243, issued on Sep. 19, 2017.
Claims priority of provisional application 62/003,395, filed on May 27, 2014.
Prior Publication US 2022/0343051 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC G06F 30/392 (2020.01) [H01L 27/0207 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first set of conductive traces in a first level of the integrated circuit, the first set of conductive traces extending in a first direction;
a second set of conductive traces in a second level of the integrated circuit different from the first level, the second set of conductive traces extending in a second direction different from the first direction, the second set of conductive traces including:
a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor; and
a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor; and
a first conductive feature extending in the second direction, being on a third level below at least the first level;
wherein the first conductive feature corresponds to at least a first contact of a first dummy transistor;
wherein the first conductive trace of the second set of conductive traces and the second conductive trace of the second set of conductive traces are separated from each other in at least the second direction;
the first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature; and
the first n-type transistor being part of a first transmission gate; and
the first p-type transistor being part of a second transmission gate.