US 11,694,012 B2
Multiplexer
Chi-Lin Liu, New Taipei (TW); Shang-Chih Hsieh, Yangmei (TW); Jian-Sing Li, Hsinchu (TW); Wei-Hsiang Ma, Taipei (TW); Yi-Hsun Chen, Hsinchu (TW); and Cheok-Kei Lei, Macau (MO)
Assigned to Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2022, as Appl. No. 17/853,095.
Application 17/853,095 is a continuation of application No. 16/883,524, filed on May 26, 2020, granted, now 11,392,743.
Claims priority of provisional application 62/861,649, filed on Jun. 14, 2019.
Prior Publication US 2022/0327275 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); H01L 27/02 (2006.01); G06F 30/392 (2020.01); G06F 30/347 (2020.01); G06F 30/39 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/347 (2020.01); G06F 30/39 (2020.01); H01L 27/0207 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multiplexer configured to receive first, second, third and fourth data signals and first, second, third and fourth select signals, and to output a selected one of the first, second, third and fourth data signals in response to the first, second, third and fourth select signals, the multiplexer comprising:
first and second fins each extending in an X-axis direction;
a first AO122 circuit including a first plurality of poly gates extending in a Y-axis direction perpendicular to the X-axis direction;
a second AO122 circuit including a second plurality of poly gates extending in the Y-axis direction;
an ND2 circuit including a third plurality of poly gates extending in the Y-axis direction, the third plurality of poly gates configured to receive first and second outputs from the first and second AO122 circuits, respectively;
wherein the second plurality of poly gates includes a first segmented gate having first and second segments separated from one another such that the first segment contacts the first fin and the second segment contacts the second fin, and wherein the first segment of the first segmented gate is configured to receive one of the first, second, third or fourth data signals, and the second segment of the first segmented gate is configured to receive one of the first, second, third or fourth select signals.