CPC G06F 30/333 (2020.01) [G01R 31/3177 (2013.01); G01R 31/31704 (2013.01); G01R 31/31813 (2013.01); G01R 31/31908 (2013.01); G01R 31/318371 (2013.01); G01R 31/318583 (2013.01)] | 20 Claims |
1. A method comprising:
identifying pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design;
splitting, by a processor, each pattern of a plurality of patterns into a first part and a second part, wherein a length of the first part is a function of a number of the identified pipeline stages; and
reformatting, by the processor, the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns.
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