US 11,694,010 B2
Reformatting scan patterns in presence of hold type pipelines
Amit Gopal M. Purohit, Bangalore (IN); Sorin Ioan Popa, Saint Ismier (FR); Denis Martin, Palo Alto, CA (US); and Paras Chhabra, Bangalore (IN)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 3, 2021, as Appl. No. 17/518,024.
Claims priority of provisional application 63/109,078, filed on Nov. 3, 2020.
Prior Publication US 2022/0137126 A1, May 5, 2022
Int. Cl. G06F 30/30 (2020.01); G06F 30/333 (2020.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3181 (2006.01); G01R 31/319 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01)
CPC G06F 30/333 (2020.01) [G01R 31/3177 (2013.01); G01R 31/31704 (2013.01); G01R 31/31813 (2013.01); G01R 31/31908 (2013.01); G01R 31/318371 (2013.01); G01R 31/318583 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design;
splitting, by a processor, each pattern of a plurality of patterns into a first part and a second part, wherein a length of the first part is a function of a number of the identified pipeline stages; and
reformatting, by the processor, the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns.