US 11,694,009 B2
Pattern centric process control
Chenmin Hu, Saratoga, CA (US); Khurram Zafar, San Jose, CA (US); Ye Chen, San Jose, CA (US); Yue Ma, San Jose, CA (US); Rong Lv, Shanghai (CN); Justin Chen, Milpitas, CA (US); Abhishek Vikram, Santa Clara, CA (US); Yuan Xu, Sunnyvale, CA (US); and Ping Zhang, Saratoga, CA (US)
Assigned to Anchor Semiconductor, Inc., Santa Clara, CA (US)
Filed by Anchor Semiconductor Inc., Santa Clara, CA (US)
Filed on Apr. 5, 2021, as Appl. No. 17/222,132.
Application 17/222,132 is a continuation of application No. 16/696,554, filed on Nov. 26, 2019, granted, now 10,997,340.
Application 16/696,554 is a continuation of application No. 15/944,080, filed on Apr. 3, 2018, granted, now 10,546,085, issued on Jan. 28, 2020.
Claims priority of provisional application 62/484,801, filed on Apr. 12, 2017.
Prior Publication US 2021/0326505 A1, Oct. 21, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/3323 (2020.01); G06F 119/18 (2020.01); G06N 5/04 (2023.01); G03F 7/00 (2006.01); G06N 20/00 (2019.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 111/10 (2020.01)
CPC G06F 30/3323 (2020.01) [G03F 7/705 (2013.01); G03F 7/70433 (2013.01); G03F 7/70441 (2013.01); G03F 7/70508 (2013.01); G06N 5/04 (2013.01); G06F 2111/04 (2020.01); G06F 2111/10 (2020.01); G06F 2111/20 (2020.01); G06F 2119/18 (2020.01); G06N 20/00 (2019.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
assigning, to a plurality of intended circuit layout patterns in a layout of a semiconductor chip, a plurality of sets of fabrication risk assessments, wherein the fabrication risk assessments in each set of fabrication risk assessments of the plurality of sets of fabrication risk assessments correspond to respective intended circuit layout patterns of the plurality of intended circuit layout patterns, the assigning comprising:
determining a first set of fabrication risk assessments based on statistical analysis of the plurality of intended circuit layout patterns; and
determining a second set of fabrication risk assessments based either on simulation of respective intended circuit layout patterns of the plurality of intended circuit layout patterns or on evaluation of empirical data for respective printed circuit layout patterns associated with respective intended circuit layout patterns of the plurality of intended circuit layout patterns;
ranking the plurality of intended circuit layout patterns based on their respective fabrication risk assessments in the plurality of sets of fabrication risk assessments; and
outputting information regarding the ranking.