US 11,694,007 B2
Automated circuit generation
Karen Mason, Sunnyvale, CA (US); and John Mason, Sunnyvale, CA (US)
Assigned to Celera, Inc., San Jose, CA (US)
Filed by Celera, Inc., San Jose, CA (US)
Filed on Oct. 21, 2021, as Appl. No. 17/507,504.
Application 17/507,504 is a continuation of application No. 16/886,544, filed on May 28, 2020, granted, now 11,361,134.
Application 16/886,544 is a continuation of application No. 16/882,217, filed on May 22, 2020.
Claims priority of provisional application 62/854,848, filed on May 30, 2019.
Prior Publication US 2022/0043953 A1, Feb. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/31 (2020.01); G06F 111/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/31 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2111/12 (2020.01)] 48 Claims
OG exemplary drawing
 
1. A computer-implemented method of generating a circuit layout comprising:
specifying a circuit schematic to be converted to said circuit layout;
receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic;
converting the circuit schematic into the plurality of layout instances; and
positioning the plurality of layout instances based on the layout script to produce said circuit layout.