US 11,693,950 B2
System and method for active cyberattack defense
Paul G Flikkema, Flagstaff, AZ (US); Bertrand F Cambou, Flagstaff, AZ (US); and James D Palmer, Flagstaff, AZ (US)
Assigned to ARIZONA BOARD OF REGENTS ON BEHALF OF NORTHERN ARIZONA UNIVERSITY, Flagstaff, AZ (US)
Filed by Arizona Board of Regents on Behalf of Northern Arizona University, Flagstaff, AZ (US)
Filed on Jun. 19, 2020, as Appl. No. 16/907,050.
Claims priority of provisional application 62/863,758, filed on Jun. 19, 2019.
Prior Publication US 2020/0401691 A1, Dec. 24, 2020
Int. Cl. G06F 21/52 (2013.01); G06F 21/12 (2013.01)
CPC G06F 21/52 (2013.01) [G06F 21/125 (2013.01); G06F 2221/033 (2013.01); G06F 2221/0724 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A computing system, comprising:
a processor configured to execute machine code instructions specified according to at least two machine code instruction formats, the processor including configuration management circuitry configured to control a machine code configuration of the processor; and memory coupled to the processor;
wherein the configuration management circuitry is configured to cause the processor to:
be able to execute, in a first configuration, instructions specified according to a first machine code instruction format and be unable to execute instructions specified according to a second machine code instruction format;
be able to execute, in a second configuration, instructions specified according to the second machine code instruction format and be unable to execute instructions specified according to the first machine code instruction format; and
wherein the computing system is configured to:
receive first machine code specifying first program code according to the first machine code instruction format;
generate second machine code specifying the first program code according to the second machine code instruction format and store the second machine code in the memory;
determine, in response to a first request to execute the first machine code, that the first machine code corresponds to a set of processor operations equivalent to processor operations to which the second machine code corresponds; and if so execute the first machine code
wherein the computing system is further configured to:
generate the second machine code while executing the first machine code;
determine, in response to a first request to execute the first machine code, that the first machine code specifies an identical set of processor operations as the second machine code; and if so
execute the first machine code.