CPC G06F 13/4282 (2013.01) [G06F 13/1689 (2013.01); G06F 2213/0026 (2013.01)] | 20 Claims |
1. A link controller comprising:
a Peripheral Component Interconnect Express (PCIe) physical layer circuit coupled to a communication link and providing a data path over said communication link;
a first data link layer controller which operates according to a PCIe protocol;
a second data link layer controller which operates according to a Gen-Z protocol;
a multiplexer-demultiplexer coupled to the first data link layer controller and the PCIe physical layer circuit; and
a protocol translation circuit coupled to the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format traffic data in a PCIe format, and passing the encapsulated traffic data to the multiplexer-demultiplexer.
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