US 11,693,724 B2
Bit error rate estimation and error correction and related systems, methods, devices
Dixon Chen, Guangdong (CN); Jiachi Yu, Guangdong (CN); and Kevin Yang, Guangdong (CN)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Oct. 16, 2019, as Appl. No. 16/654,739.
Claims priority of application No. 201910784043.6 (CN), filed on Aug. 23, 2019.
Prior Publication US 2021/0055980 A1, Feb. 25, 2021
Int. Cl. G06F 11/07 (2006.01); G06F 11/32 (2006.01); G06F 11/16 (2006.01); H04L 1/20 (2006.01); H04L 25/49 (2006.01); H03M 5/12 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 11/0793 (2013.01); G06F 11/1608 (2013.01); G06F 11/322 (2013.01); H03M 5/12 (2013.01); H04L 1/20 (2013.01); H04L 1/205 (2013.01); H04L 25/4904 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A physical layer device, comprising:
an input to receive a signal from a shared transmission medium of a wired local area network, the shared transmission medium of the wired local area network comprising a physical medium that is a communication path between nodes that are part of the wired local area network, the nodes including respective instances of physical layer devices; and
one or more processors to, at the physical layer device and in a physical layer of an Open Systems Interconnection (OSI) model:
identify coding violations in the signal received via the shared transmission medium of the wired local area network, the coding violations including two-level differential Manchester Encoding (DME) violations wherein signal transitions are not detected at respective clock transitions;
determine a rate of the coding violations in the signal; and
estimate a bit error rate of the signal to be the determined rate of the coding violations.