US 11,693,691 B2
Systems, methods, and apparatuses for heterogeneous computing
Rajesh M. Sankaran, Portland, OR (US); Gilbert Neiger, Hillsboro, OR (US); Narayan Ranganathan, Bangalore (IN); Stephen R. Van Doren, Portland, OR (US); Joseph Nuzman, Haifa (IL); Niall D. McDonnell, Limerick (IE); Michael A. O'Hanlon, Limerick (IE); Lokpraveen B. Mosur, Gilbert, AZ (US); Tracy Garrett Drysdale, Paradise Valley, AZ (US); Eriko Nurvitadhi, Hillsboro, OR (US); Asit K. Mishra, Hillsboro, OR (US); Ganesh Venkatesh, Hillsboro, OR (US); Deborah T. Marr, Portland, OR (US); Nicholas P. Carter, Somerville, MA (US); Jonathan D. Pearce, Hillsboro, OR (US); Edward T. Grochowski, San Jose, CA (US); Richard J. Greco, Hillsboro, OR (US); Robert Valentine, Kiryat Tivon (IL); Jesus Corbal, King City, OR (US); Thomas D. Fletcher, Sherwood, OR (US); Dennis R. Bradford, Portland, OR (US); Dwight P. Manley, Holliston, MA (US); Mark J. Charney, Lexington, MA (US); Jeffrey J. Cook, Portland, OR (US); Paul Caprioli, Hillsboro, OR (US); Koichi Yamada, Los Gatos, CA (US); Kent D. Glossop, Merrimack, NH (US); and David B. Sheffield, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 21, 2021, as Appl. No. 17/381,521.
Application 17/381,521 is a continuation of application No. 16/913,265, filed on Jun. 26, 2020, granted, now 11,093,277.
Application 16/913,265 is a continuation of application No. 16/474,978, granted, now 11,416,281, previously published as PCT/US2016/069640, filed on Dec. 31, 2016.
Prior Publication US 2022/0164218 A1, May 26, 2022
Int. Cl. G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/48 (2013.01) [G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 9/30036 (2013.01); G06F 9/383 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A system comprising:
a multi-chip package substrate;
a plurality of heterogeneous dies mounted on the multi-chip package substrate, the heterogeneous dies including:
a plurality of data processing dies, a data processing die comprising:
a first on-chip communication fabric,
a plurality of cores coupled to the first on-chip communication fabric to execute instructions and process data, and
a first serializer/de-serializer (“SerDes”) interconnect coupled to the first on-chip communication fabric, the first SerDes interconnect to communicate over a first one or more data lanes;
an input/output (TO) and memory interconnect die to couple the plurality of cores to a system memory device and one or more IO devices, the IO and memory interconnect die comprising:
a second SerDes interconnect coupled to a second one or more data lanes,
the second SerDes interconnect comprising:
a modular physical layer (PHY) block;
a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols, the plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate first data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate second data in accordance with a second data communication protocol; and
a multiplexer configurable to couple the protocol specific logic blocks to the PHY block;
wherein the first data communication protocol comprises an IO protocol;
a second on-chip communication fabric;
a third SerDes interconnect to communicate over the first one or more data lanes;
a memory controller to couple the plurality of cores to the system memory device; and
an IO memory management unit (IOMMU) coupled to the second on-chip communication fabric, the IOMMU to manage memory accesses on behalf of one or more IO devices coupled to at least one data lane of the second one or more data lanes, the IOMMU to perform virtual-to-physical address translations for memory access requests received over the at least one data lane.