CPC G06F 9/3836 (2013.01) [G06F 8/433 (2013.01); G06F 8/451 (2013.01); G06F 9/3867 (2013.01)] | 17 Claims |
1. A method for operating a multistage programmable processing pipeline circuit, the method comprising:
compiling a set of instructions for a stage of the multistage programmable packet processing pipeline circuit that is executed in response to receiving a packet header vector (PHV) corresponding to a packet, wherein the stage of the multistage programmable packet processing pipeline circuit includes a match-action unit with multiple match processing units (MPUs) configured to process instructions in parallel and wherein the processing of all instructions in the set of instructions is completed before processing of the packet proceeds to the next stage in the multistage programmable packet processing pipeline circuit, wherein compiling the set of instructions includes:
identifying first and second subsets of instructions within the set of instructions that are able to be executed independent of each other, wherein the set of instructions corresponds to an action that is identified by a lookup in the match-action unit using PHV;
assigning the first subset of instructions to a first MPU in the match-action unit of the stage;
assigning the second subset of instructions to a second MPU in the match-action unit of the stage; and
wherein the first and second subsets of instructions are to be executed in parallel at the first and second MPU of the match-action unit, respectively.
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