CPC G06F 9/3812 (2013.01) [G06F 7/4806 (2013.01); G06F 8/4436 (2013.01); G06F 17/142 (2013.01)] | 8 Claims |
1. A method for configuring a reduced instruction set computer processor architecture to process a Discrete Fourier Transform (DFT) of a finite-length sequence N, wherein the computer processor architecture includes a plurality of primary processing cores, each primary processing core comprising a local memory, and a plurality of arithmetic logic units, each primary processing core having an associated node wrapper, the associated node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:
(a) applying a Decimation-in-Frequency algorithm to the DFT to decompose the DFT of a finite-length sequence N into two derived DFTs each of a length N/2;
(b) constructing a logic element equivalent of each stage of the derived DFTs in which inputs and outputs are composed of real and imaginary components;
(c) repeating (a) and (b) for each stage of the DFT except for the endpoint stages of the DFT, wherein the endpoint stages are a first stage of the DFT and a last stage of the DFT;
(d) for each stage of the DFT configuring the logic elements to provide all of the required inputs and outputs of the DFT and, for each endpoint, configuring a logic element equivalent of the corresponding stage of the derived DFTs in which inputs to the first stage and outputs of the last stage are composed of only real components;
(e) configuring at least one primary processing core of the computer processor architecture to implement the logic element equivalents of each stage of the derived DFTs in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the local memory and other ones of the plurality arithmetic logic units; and
(f) configuring the computer processor architecture to couple the output of each stage on the DFT to the input of a subsequent stage.
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