US 11,693,662 B2
Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm
Morris Jacob Creeger, Santa Clara, CA (US); Tianfang Liu, Santa Clara, CA (US); Frederick Furtek, Santa Clara, CA (US); and Paul L. Master, Santa Clara, CA (US)
Assigned to CORNAMI INC., Campbell, CA (US)
Filed by Cornami Inc., Santa Clara, CA (US)
Filed on Jan. 15, 2020, as Appl. No. 16/743,257.
Application 16/743,257 is a continuation in part of application No. 15/970,915, filed on May 4, 2018, granted, now 11,294,851.
Claims priority of provisional application 62/883,967, filed on Aug. 7, 2019.
Prior Publication US 2020/0213079 A1, Jul. 2, 2020
Int. Cl. G06F 7/48 (2006.01); G06F 17/14 (2006.01); G06F 9/38 (2018.01); G06F 8/41 (2018.01)
CPC G06F 9/3812 (2013.01) [G06F 7/4806 (2013.01); G06F 8/4436 (2013.01); G06F 17/142 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for configuring a reduced instruction set computer processor architecture to process a Discrete Fourier Transform (DFT) of a finite-length sequence N, wherein the computer processor architecture includes a plurality of primary processing cores, each primary processing core comprising a local memory, and a plurality of arithmetic logic units, each primary processing core having an associated node wrapper, the associated node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:
(a) applying a Decimation-in-Frequency algorithm to the DFT to decompose the DFT of a finite-length sequence N into two derived DFTs each of a length N/2;
(b) constructing a logic element equivalent of each stage of the derived DFTs in which inputs and outputs are composed of real and imaginary components;
(c) repeating (a) and (b) for each stage of the DFT except for the endpoint stages of the DFT, wherein the endpoint stages are a first stage of the DFT and a last stage of the DFT;
(d) for each stage of the DFT configuring the logic elements to provide all of the required inputs and outputs of the DFT and, for each endpoint, configuring a logic element equivalent of the corresponding stage of the derived DFTs in which inputs to the first stage and outputs of the last stage are composed of only real components;
(e) configuring at least one primary processing core of the computer processor architecture to implement the logic element equivalents of each stage of the derived DFTs in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the local memory and other ones of the plurality arithmetic logic units; and
(f) configuring the computer processor architecture to couple the output of each stage on the DFT to the input of a subsequent stage.