US 11,693,661 B2
Mechanism for interrupting and resuming execution on an unprotected pipeline processor
Timothy D. Anderson, University Park, TX (US); Joseph Zbiciak, San Jose, CA (US); and Kai Chirca, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 27, 2021, as Appl. No. 17/241,198.
Application 15/429,205 is a division of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Application 17/241,198 is a continuation of application No. 16/384,434, filed on Apr. 15, 2019, granted, now 10,990,398.
Application 16/384,434 is a continuation in part of application No. 16/227,238, filed on Dec. 20, 2018, granted, now 11,036,648.
Application 16/227,238 is a continuation of application No. 15/429,205, filed on Feb. 10, 2017, granted, now 10,162,641, issued on Dec. 25, 2018.
Claims priority of provisional application 62/786,471, filed on Dec. 30, 2018.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2021/0247980 A1, Aug. 12, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); G06F 9/32 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 11/00 (2006.01); G06F 9/345 (2018.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30123 (2013.01); G06F 9/30145 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 9/3861 (2013.01); G06F 9/3867 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit device comprising:
a functional unit that includes a set of pipeline stages configured to collectively execute a first instruction;
a local capture queue coupled to the functional unit that includes a set of registers, wherein each register of the set of registers is coupled to a respective stage of the set of pipeline stages to store a respective intermediate result of the first instruction; and
a scoreboard coupled to the functional unit and the local capture queue and configured to:
based on receiving the first instruction, set a lifetime tracking value based on an expected duration of execution of the first instruction;
adjust the lifetime tracking value during the execution of the first instruction by the set of pipeline stages; and
in response to a second instruction, preempt the first instruction by:
causing a first register of the local capture queue to store a first intermediate result of the first instruction from a first stage of the set of pipeline stages; and
based on the second instruction having completed, using the lifetime tracking value to restore the first intermediate result to the set of pipeline stages.