CPC G06F 9/3001 (2013.01) [G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/3893 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01); G06F 2207/4824 (2013.01)] | 20 Claims |
1. A compute apparatus comprising:
a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network, wherein the ternary weight represents a weight value of one of positive one, zero, and negative one; and
an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
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