CPC G06F 8/34 (2013.01) [G06F 8/433 (2013.01); G06F 8/443 (2013.01); G06F 9/4494 (2018.02); G06F 15/82 (2013.01)] | 24 Claims |
1. An apparatus to optimize hardware execution efficiency, the apparatus comprising:
backedge identifier circuitry to identify a backedge of a data flow graph, the data flow graph representative of input code;
buffer inserter circuitry to:
determine an optimization goal for the data flow graph based on a resource characteristic of a configurable spatial accelerator; and
insert a quantity of buffers into the data flow graph, the quantity of buffers based on the optimization goal; and
compiler circuitry to generate output code based on the data flow graph.
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