US 11,693,633 B2
Methods and apparatus to detect and annotate backedges in a dataflow graph
Kermin E. ChoFleming, Jr., Hudson, MA (US); Jesmin Jahan Tithi, San Jose, CA (US); Joshua Cranmer, Hudson, MA (US); and Suresh Srinivasan, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2021, as Appl. No. 17/341,086.
Application 17/341,086 is a continuation of application No. 16/370,935, filed on Mar. 30, 2019, granted, now 11,029,927.
Prior Publication US 2021/0365248 A1, Nov. 25, 2021
Int. Cl. G06F 8/34 (2018.01); G06F 9/448 (2018.01); G06F 8/41 (2018.01); G06F 15/82 (2006.01)
CPC G06F 8/34 (2013.01) [G06F 8/433 (2013.01); G06F 8/443 (2013.01); G06F 9/4494 (2018.02); G06F 15/82 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus to optimize hardware execution efficiency, the apparatus comprising:
backedge identifier circuitry to identify a backedge of a data flow graph, the data flow graph representative of input code;
buffer inserter circuitry to:
determine an optimization goal for the data flow graph based on a resource characteristic of a configurable spatial accelerator; and
insert a quantity of buffers into the data flow graph, the quantity of buffers based on the optimization goal; and
compiler circuitry to generate output code based on the data flow graph.