US 11,693,588 B2
Precise longitudinal monitoring of memory operations
Ahmad Yasin, Haifa (IL); Michael Chynoweth, Placitas, NM (US); Rajshree Chabukswar, Sunnyvale, CA (US); and Muhammad Taher, Umm El Fahm (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 21, 2020, as Appl. No. 15/929,272.
Application 15/929,272 is a continuation of application No. 16/177,642, filed on Nov. 1, 2018, granted, now 10,649,688.
Prior Publication US 2020/0249866 A1, Aug. 6, 2020
Int. Cl. G06F 3/06 (2006.01); G06F 11/34 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/3466 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a memory subsystem comprising a first memory subunit;
an execution engine unit coupled to the memory subsystem, the execution engine unit to:
select a load operation to monitor;
determine an identifier of the load operation; and
transmit the identifier to the memory subsystem; and
wherein, responsive to receipt of the identifier, the first memory subunit is to store a piece of information, related to a status of the load operation; and
logic coupled to the memory subsystem, the logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer, the memory information comprising auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information stored in a particular field of the memory-related fields.