US 11,693,582 B2
Automatic read calibration operations
Aliasgar S. Madraswala, Folsom, CA (US); Ali Khakifirooz, Brookline, MA (US); Camila Jaramillo, San Jose, CA (US); John Egler, Folsom, CA (US); Netra Mahuli, Folsom, CA (US); Renjie Chen, San Jose, CA (US); and Yogesh Wakchaure, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 7, 2020, as Appl. No. 16/947,592.
Prior Publication US 2022/0043596 A1, Feb. 10, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory cells;
a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and
a controller to:
transpose a value indicative of a voltage of the first cell to the sense node;
isolate the sense node from the bitline;
calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter; and
store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.