CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a plurality of memory cells;
a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and
a controller to:
transpose a value indicative of a voltage of the first cell to the sense node;
isolate the sense node from the bitline;
calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter; and
store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.
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