US 11,693,567 B2
Memory performance optimization method, memory control circuit unit and memory storage device
Qi-Ao Zhu, Anhui (CN); Jing Zhang, Anhui (CN); Kuai Cao, Anhui (CN); Xin Wang, Anhui (CN); Xu Hui Cheng, Anhui (CN); and Dong Sheng Rao, Hefei (CN)
Assigned to Hefei Core Storage Electronic Limited, Anhui (CN)
Filed by Hefei Core Storage Electronic Limited, Anhui (CN)
Filed on Nov. 22, 2021, as Appl. No. 17/533,020.
Claims priority of application No. 202111231508.9 (CN), filed on Oct. 22, 2021.
Prior Publication US 2023/0127512 A1, Apr. 27, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 1/3287 (2019.01); G06F 13/16 (2006.01); G06F 1/3234 (2019.01)
CPC G06F 3/0625 (2013.01) [G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 3/0634 (2013.01); G06F 3/0653 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory performance optimization method for a memory storage device, the memory storage device comprising a memory control circuit unit and a rewritable non-volatile memory module, the memory control circuit unit comprising a buffer memory, and the method comprising:
counting an idle time of the memory storage device in an active mode;
instructing the memory storage device to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold;
counting a first waiting time of the memory storage device in the first low electricity consumption mode;
instructing the memory storage device to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold, wherein electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode;
counting a second waiting time of the memory storage device in the first low electricity consumption mode in response to a condition for performing a background operation being met;
instructing the memory storage device to enter a background mode from the first low electricity consumption mode in response to the second waiting time being greater than a second waiting threshold;
instructing the memory storage device to enter the first low electricity consumption mode from the background mode after the background operation being performed, and counting a third waiting time of the memory storage device in the first low electricity consumption mode; and
instructing the memory storage device to enter the second low electricity consumption mode from the first low electricity consumption mode in response to the third waiting time being greater than a third waiting threshold, wherein the third waiting threshold is equal to the first waiting threshold minus the second waiting threshold.