US 11,690,227 B2
Method of forming high-voltage transistor with thin gate poly
Chun Chen, San Jose, CA (US); James Pak, Sunnyvale, CA (US); Unsoon Kim, San Jose, CA (US); Inkuk Kang, San Jose, CA (US); Sung-Taeg Kang, Palo Alto, CA (US); and Kuo Tung Chang, Saratoga, CA (US)
Assigned to CYPRESS SEMICONDUCTOR CORPORATION, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on May 18, 2021, as Appl. No. 17/323,819.
Application 17/323,819 is a continuation of application No. 16/292,042, filed on Mar. 4, 2019, abandoned.
Application 16/292,042 is a continuation of application No. 15/848,327, filed on Dec. 20, 2017, granted, now 10,242,996, issued on Mar. 26, 2019.
Claims priority of provisional application 62/534,463, filed on Jul. 19, 2017.
Prior Publication US 2021/0296343 A1, Sep. 23, 2021
Int. Cl. H01L 21/28 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 43/40 (2023.01); H10B 41/30 (2023.01); H10B 41/49 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01)
CPC H10B 43/40 (2023.02) [H01L 21/26513 (2013.01); H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/456 (2013.01); H01L 29/4933 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/7833 (2013.01); H01L 29/792 (2013.01); H10B 41/30 (2023.02); H10B 41/49 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H01L 29/517 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device comprising:
forming a charge trapping stack over a surface of a substrate in a memory region;
forming a gate dielectric over the surface of the substrate in a peripheral region;
depositing a first polysilicon layer and a height-enhancing (HE) film over the surface of the substrate in the memory region and the peripheral region;
patterning the HE film, first polysilicon layer, and the charge trapping stack to form a memory-gate in the memory region;
patterning the HE film, first polysilicon layer, and the gate dielectric in a high voltage (HV) area in the peripheral region to form a HV-gate;
depositing a second polysilicon layer over the surface of the substrate;
planarizing the second polysilicon layer to remove portions of the second polysilicon layer extending above the memory-gate and HV-gate; and
implanting ions to form a first source/drain (S/D) region in the substrate adjacent to the HV-gate, wherein the first S/D region comprises the ions implanted to a depth in the substrate greater than a height of the HV-gate above the surface of the substrate.