US 11,690,215 B2
Self-aligned bitline and capacitor via formation
Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Tahir Ghani, Portland, OR (US); Yih Wang, Portland, OR (US); Benjamin Chu-Kung, Portland, OR (US); and Shriram Shivaraman, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 2, 2018, as Appl. No. 15/943,576.
Prior Publication US 2019/0304982 A1, Oct. 3, 2019
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/34 (2023.02) [H10B 12/03 (2023.02); H10B 12/36 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
15. A DRAM memory cell structure, comprising:
a bottom gate;
a dielectric formed above the bottom gate;
channel material formed above the dielectric comprising a first portion that is parallel to the gate and second and third portions that are orthogonal to the gate;
a capacitor landing structure coupled to the second portion of the channel material; and
a bitline coupled to the third portion of the channel material wherein the capacitor landing structure is extends above the bitline, and wherein the capacitor landing structure has a bottommost surface at a same level as a bottommost surface of the bitline.