US 11,690,209 B2
Fin-based well straps for improving memory macro performance
Chih-Chuan Yang, Hsinchu (TW); Kuo-Hsiu Hsu, Taoyuan County (TW); Feng-Ming Chang, Hsinchu County (TW); Wen-Chun Keng, Hsinchu (TW); and Lien Jung Hung, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 4, 2020, as Appl. No. 16/984,983.
Claims priority of provisional application 62/907,565, filed on Sep. 28, 2019.
Prior Publication US 2021/0098469 A1, Apr. 1, 2021
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a first FinFET disposed over a doped region of a first type dopant, wherein the first FinFET includes a first fin structure and first source/drain (S/D) features, the first fin structure having a first width;
a second FinFET disposed over the doped region, wherein the second FinFET includes a second fin structure and second source/drain (S/D) features, the second fin structure having a second width;
a fin-based well strap disposed over the doped region, wherein the fin-based well strap includes a third fin structure and third S/D features, the third fin structure having a third width that is larger than either of the first width or the second width, wherein the fin-based well strap is configured to bias the doped region to a bias voltage;
a first fin stub connecting a bottom portion of the first fin structure with a bottom portion of the third fin structure; and
a second fin stub connecting a bottom portion of the second fin structure with the bottom portion of the third fin structure.