US 11,690,167 B2
Printed circuit board and electronic device including same
Eunseok Hong, Suwon-si (KR); Gyounghwan Park, Suwon-si (KR); and Cheolyoon Chung, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 21, 2020, as Appl. No. 16/880,703.
Claims priority of application No. 10-2019-0106670 (KR), filed on Aug. 29, 2019.
Prior Publication US 2021/0068247 A1, Mar. 4, 2021
Int. Cl. H05K 1/02 (2006.01); H05K 1/18 (2006.01); H04N 25/70 (2023.01)
CPC H05K 1/0245 (2013.01) [H04N 25/70 (2023.01); H05K 1/028 (2013.01); H05K 1/0218 (2013.01); H05K 1/181 (2013.01); H05K 2201/093 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/10121 (2013.01); H05K 2201/10128 (2013.01); H05K 2201/10151 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A printed circuit board comprising: a first wiring layer comprising a plurality of first signal lines and a plurality of first dummy lines; and a second wiring layer arranged on the first wiring layer and comprising a plurality of second signal lines and a plurality of second dummy lines, wherein when the printed circuit board is viewed from above, each of the plurality of first signal lines is arranged to overlap, at least in part, one of the plurality of second dummy lines, and the plurality of second signal lines is arranged to overlap, at least in part, one of the plurality of first dummy lines, and wherein the printed circuit board is configured to provide a plurality of 3-phase interfaces by combining one of the plurality of first signal lines with two of the plurality of second signal lines adjacent thereto to form a first 3-phase interface and combining one of the plurality of second signal lines with two of the plurality of first signal lines adjacent thereto to form a second 3-phase interface, and wherein a first distance between the first signal line and the second signal line included in any one of the first 3-phase interface and the second 3-phase interface is smaller than a second distance between the second signal line of the second 3-phase interface and the first signal line of the first 3-phase interface.