CPC H04W 24/02 (2013.01) [H04W 8/082 (2013.01); H04W 16/16 (2013.01); H04W 16/18 (2013.01); H04W 16/22 (2013.01); H04W 24/04 (2013.01); H04W 28/16 (2013.01); H04W 48/10 (2013.01); H04W 48/12 (2013.01); H04W 48/18 (2013.01); H04W 80/02 (2013.01); H04W 84/045 (2013.01); H04W 88/085 (2013.01); H04W 88/18 (2013.01)] | 18 Claims |
1. A non-transitory machine readable memory encoded with instructions which, when executed by one or more processors, cause the one or more processors to perform a process, comprising:
determining a demand for connectivity to a wireless communications access network;
determining a combination of radio access network component modules based on the demand for connectivity, the combination of radio access network component modules including at least one baseband module and at least one of a plurality of functionally separate interface/router components, each of which are configured to perform communications with a corresponding one of a plurality of external, core network components;
determining a plurality of interconnect channels between the at least one baseband module and the at least one interface/router component;
instantiating each component module within the radio access network combination of component modules;
connecting the at least one baseband module to at least one external, core network component via the at least one interface/router component to which the at least one external, core network component corresponds; and
connecting the at least one baseband module to at least one user equipment (UE).
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