CPC H04L 51/222 (2022.05) [H04L 51/212 (2022.05); H04L 51/214 (2022.05); H04L 51/226 (2022.05); G06Q 10/107 (2013.01)] | 14 Claims |
1. A method comprising:
in a system comprising at least one processor operatively coupled to a non-transitory memory storing computer-readable instructions that, when executed by the at least one processor, causes the system to perform the steps of:
intercepting, via a system input interface, a first incoming message and a second incoming message, each having respective destinations other than the system;
determining, based on one or more first internet protocol (IP) attributes of the first incoming message, that the first incoming message originated from a first participant device associated with a first configuration;
determining, based on one or more second IP attributes of the second incoming message, that the second incoming message originated from a second participant device associated with a second configuration;
determining one or more transmission delay offsets according to one or more of the first configuration and the second configuration; and
applying the one or more transmission delay offsets to one or more of the first incoming message and the second incoming message prior to transmission of each from the system to their respective destinations.
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