US 11,689,443 B2
Chip to chip network routing using DC bias and differential signaling
Robert Wiser, Santa Cruz, CA (US); Venkat Mattela, San Jose, CA (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Redpine Signals, Inc., San Jose, CA (US)
Filed on May 29, 2021, as Appl. No. 17/334,703.
Prior Publication US 2022/0385565 A1, Dec. 1, 2022
Int. Cl. H04L 45/02 (2022.01)
CPC H04L 45/08 (2013.01) 19 Claims
OG exemplary drawing
 
1. A node fabric for machine learning, the node fabric comprising:
an originating node having a plurality of communication interfaces, each communication interface of the originating node having an input and an output;
a plurality of node groups, each node group comprising a plurality of nodes and having at least one communication interface of the plurality of nodes coupled to a communication interface of the originating node, each communications interface of a node in a node group having an input and an output;
each node of a node group having a route table initialized with a correspondence between an incoming DC voltage applied to a communication interface input and either an communication interface output or a local termination;
the originating node sending a DC voltage superimposed with a differential signal to a node group;
where each node of a node group which receives the DC voltage and differential signal is configured to associate the DC voltage with a communication interface from the route table, a node of the node group which receives the DC voltage and differential signal thereafter coupling the DC voltage and differential signal to the associated communication interface output or local termination.