CPC H03M 3/04 (2013.01) [G06J 1/00 (2013.01); H03M 1/38 (2013.01); H03K 19/20 (2013.01)] | 21 Claims |
1. Multiplier-accumulator (MAC) with Analog to Digital Converter (ADC) comprising:
a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
a first plurality of MAC unit elements (MAC UEs) performing multiply-accumulate operations on X and W digital inputs, each MAC UE providing a multiplication result as a binary weighted charge transferred to the differential charge transfer bus;
a second plurality of Bias unit elements (Bias UEs) having a bias digital input and coupled to the differential charge transfer bus, each Bias UE placing a bias value as a binary weighted charge onto the differential charge transfer bus according to the bias digital input;
a third plurality of ADC unit elements (ADC UEs) arranged in a binary sequence of ADC UE groups, at least one subsequent group of ADC UEs having twice the number of ADC UEs as a previous group of ADC UEs, each ADC UE operative to add or subtract charge present on the differential charge transfer bus;
a successive approximation register (SAR) controller coupled to the comparison output and to a plurality of registers, each register coupled to a corresponding group of SAR-UEs and causing each corresponding group of SAR UEs to transfer or remove charge on the differential charge transfer bus until a number of bits equal to a number of registers in the plurality of registers has shifted through the plurality of registers, thereby generating a digital MAC output.
|