US 11,688,813 B2
Method of fabricating semiconductor device
Seung Mo Kang, Suwon-si (KR); Moon Seung Yang, Suwon-si (KR); Jongryeol Yoo, Suwon-si (KR); Sihyung Lee, Suwon-si (KR); Sunguk Jang, Suwon-si (KR); and Eunhye Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 26, 2022, as Appl. No. 17/584,545.
Application 17/584,545 is a continuation of application No. 16/774,653, filed on Jan. 28, 2020, granted, now 11,251,313.
Claims priority of application No. 10-2019-0062553 (KR), filed on May 28, 2019.
Prior Publication US 2022/0149210 A1, May 12, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/02664 (2013.01); H01L 21/311 (2013.01); H01L 21/3247 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
forming a stack structure that includes a plurality of semiconductor patterns and a plurality of sacrificial patterns that are alternately stacked on a semiconductor substrate;
forming a dummy gate electrode that runs across the stack structure and a gate spacer that covers a sidewall of the dummy gate electrode, wherein a portion of the stack structure is exposed outside the gate spacer;
removing the portion of the stack structure exposed outside the gate spacer to form a spacer opening that exposes the stack structure below the dummy gate electrode; and
forming a first source/drain pattern that covers a lateral surface of the stack structure exposed to the spacer opening,
wherein forming the first source/drain pattern includes:
performing a selective epitaxial growth process to form the first source/drain pattern having a first sidewall profile; and
performing a reflow process to change the first sidewall profile of the first source/drain pattern into a second sidewall profile.