US 11,688,811 B2
Transistor comprising a channel placed under shear strain and fabrication process
Emmanuel Augendre, Montbonnot (FR); Maxime Argoud, La Chapelle de la Tour (FR); Sylvain Maitrejean, Grenoble (FR); Pierre Morin, Albany, NY (US); and Raluca Tiron, Saint-Martin-le-Vinoux (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Dec. 16, 2020, as Appl. No. 17/123,231.
Application 17/123,231 is a division of application No. 14/978,778, filed on Dec. 22, 2015, granted, now 10,978,594.
Claims priority of application No. 1463176 (FR), filed on Dec. 23, 2014.
Prior Publication US 2021/0104634 A1, Apr. 8, 2021
Int. Cl. H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 29/1033 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/7842 (2013.01); H01L 29/78654 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A process for fabricating a field-effect transistor including an active zone comprising a source, a channel, a drain, and a control gate, which is positioned level with said channel, allowing a flow of charge carriers in the channel to be controlled, comprising the following steps:
producing the field-effect transistor including the source, the channel, the drain and a sacrificial gate above the channel, the channel being compressively or tensilely strained;
depositing a dielectric layer to encapsulate the field-effect transistor with a dielectric;
selectively etching the sacrificial gate so as to define a gate cavity through the encapsulating dielectric layer;
depositing a block copolymer layer comprising a first species and a second species in the gate cavity having a source-side first internal wall and a drain-side second internal wall;
removing the first or second species so as to define masking patterns positioned facing at least one of the walls and opening onto the bottom of the gate cavity;
producing one or more perforations in the channel facing said wall or said walls;
depositing at least one gate material in the gate cavity facing the perforated channel,
wherein the process comprises the depositing of a neutralizing layer prior to the deposition of the block copolymer layer, so as to allow the one or more perforations in the channel to be given a preferred orientation.