US 11,688,809 B2
Semiconductor device structure
Kuo-Cheng Ching, Hsinchu County (TW); Kuan-Ting Pan, Taipei (TW); Kuan-Lun Cheng, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Apr. 17, 2021, as Appl. No. 17/233,451.
Application 17/233,451 is a continuation of application No. 16/859,779, filed on Apr. 27, 2020, granted, now 10,985,277.
Application 16/859,779 is a continuation of application No. 15/629,885, filed on Jun. 22, 2017, granted, now 10,636,910, issued on Apr. 28, 2020.
Claims priority of provisional application 62/512,715, filed on May 30, 2017.
Prior Publication US 2021/0234036 A1, Jul. 29, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/16 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/16 (2013.01); H01L 29/1608 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a fin structure protruding above a substrate;
a semiconductive capping layer wrapping around three sides of a channel region of the fin structure;
an oxide layer wrapping around three sides of the semiconductive capping layer, wherein a thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer; and
a gate structure wrapping around three sides of the oxide layer.