US 11,688,787 B2
Semiconductor device having modified profile metal gate
Yu-Lien Huang, Hsinchu County (TW); Chi-Wen Liu, Hsinchu (TW); Clement Hsingjen Wann, Carmel, NY (US); Ming-Huan Tsai, Hsinchu County (TW); and Zhao-Cheng Chen, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 5, 2021, as Appl. No. 17/301,467.
Application 14/952,733 is a division of application No. 13/745,205, filed on Jan. 18, 2013, granted, now 9,202,691, issued on Dec. 1, 2015.
Application 17/301,467 is a continuation of application No. 16/572,438, filed on Sep. 16, 2019, granted, now 10,971,594.
Application 16/572,438 is a continuation of application No. 15/614,274, filed on Jun. 5, 2017, granted, now 10,418,456, issued on Sep. 17, 2019.
Application 15/614,274 is a continuation of application No. 14/952,733, filed on Nov. 25, 2015, granted, now 9,673,292, issued on Jun. 6, 2017.
Prior Publication US 2021/0226029 A1, Jul. 22, 2021
Int. Cl. H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/4966 (2013.01) [H01L 21/02697 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 29/517 (2013.01); H01L 29/7833 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a top surface; and
a gate structure disposed over the semiconductor substrate, wherein the gate structure includes:
a gate dielectric layer of a substantially U-shaped configuration and extending to a first height above the top surface, wherein the substantially U-shaped configuration has a bottom portion, a first side portion extending up from a first end of the bottom portion and a second side portion extending up from a second end of the bottom portion;
a first metal layer directly on the gate dielectric layer, wherein the first metal layer interfaces a top surface of the bottom portion, a first portion of a sidewall of the first side portion, and a second portion of a sidewall of the second side portion; and
a second metal layer over the first metal layer and extending to a second height above the top surface, wherein the second height is greater than the first height, and wherein the second metal layer interfaces a top surface of the first side portion and a top surface of the second side portion of the gate dielectric layer.