US 11,688,764 B2
Semiconductor structure and method of forming same
Yu-Cheng Tung, Kaohsiung (TW); Yun-Fan Chou, Taichung (TW); Te-Hao Huang, Hsinchu County (TW); Hsien-Shih Chu, Kaohsiung (TW); and Feng-Ming Huang, Pingtung County (TW)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Sep. 2, 2021, as Appl. No. 17/465,803.
Application 17/465,803 is a division of application No. 16/635,208, granted, now 11,145,715, previously published as PCT/CN2019/124588, filed on Dec. 11, 2019.
Claims priority of application No. 201910591043.4 (CN), filed on Jul. 2, 2019.
Prior Publication US 2021/0399092 A1, Dec. 23, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/762 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a trench isolation structure formed in an isolation trench in a substrate, wherein at least part of a top surface of the trench isolation structure is lower than a top surface of the substrate;
an electrically conductive structure formed over the trench isolation structure in the substrate and filling the isolation trench, the electrically conductive structure comprising a first conductive layer and a second conductive layer, the first conductive layer filling the isolation trench and extending beyond the isolation trench, the second conductive layer formed on the first conductive layer, each of the first and second conductive layers having a top surface portion that is in correspondence with the isolation trench and defines a recess; and
a masking layer formed on the second conductive layer of the electrically conductive structure, wherein a portion of the masking layer corresponding with the recess in the second conductive layer delimits a void with the recess in the second conductive layer.