US 11,688,740 B2
Semiconductor device
Taehyung Kim, Hwaseong-si (KR); Jinwoo Jeong, Suwon-si (KR); Jiwook Kwon, Daejeon (KR); Raheel Azmat, Suwon-si (KR); and Kwanyoung Chun, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 10, 2022, as Appl. No. 17/740,900.
Application 17/740,900 is a continuation of application No. 16/864,260, filed on May 1, 2020, granted, now 11,348,918.
Claims priority of application No. 10-2019-0102583 (KR), filed on Aug. 21, 2019.
Prior Publication US 2022/0271034 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H10B 10/00 (2023.01)
CPC H01L 27/0922 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H10B 10/125 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a first active pattern and a second active pattern that are adjacent to each other in a first direction;
a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern including a plurality of first semiconductor patterns that are stacked on the first active pattern and spaced apart from each other, the plurality of first semiconductor patterns being connected to the first source/drain pattern;
a second channel pattern and a second source/drain pattern on the second active pattern, the second channel pattern including a plurality of second semiconductor patterns that are stacked on the second active pattern and spaced apart from each other, the plurality of second semiconductor patterns being connected to the second source/drain pattern;
a gate electrode on the first channel pattern and the second channel pattern, the gate electrode extending in the first direction;
a first power rail electrically connected to the first source/drain pattern; and
a second power rail electrically connected to the second source/drain pattern,
wherein the second power rail vertically overlaps the second portion of the gate electrode,
wherein the gate electrode includes:
a first portion between adjacent ones of the plurality of first semiconductor patterns; and
a second portion between adjacent ones of the plurality of second semiconductor patterns, and
wherein a width of the second portion in the first direction is at least two times a width of the first portion in the first direction.