US 11,688,736 B2
Multi-gate device and related methods
Li-Yang Chuang, Hsinchu (TW); Jia-Chuan You, Taoyuan County (TW); Kuo-Cheng Chiang, Hsinchu County (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 4, 2022, as Appl. No. 17/657,941.
Application 17/657,941 is a continuation of application No. 16/947,377, filed on Jul. 30, 2020, granted, now 11,296,082.
Prior Publication US 2022/0231016 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 29/0665 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01); H01L 29/7855 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
etching a metal layer from a dummy gate structure disposed at an active edge, wherein the etching the metal layer removes the metal layer from between adjacent channel layers, and wherein a gate dielectric layer of the dummy gate structure remains disposed between the adjacent channel layers after removal of the metal layer; and
after etching the metal layer from the dummy gate structure, forming a cut region along the active edge, wherein a portion of the gate dielectric layer remains disposed at a channel layer-inner spacer interface after formation of the cut region.