US 11,688,721 B2
Chip package structure and manufacturing method thereof
XinRu Zeng, Wuhan (CN); Peng Chen, Wuhan (CN); and Houde Zhou, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Aug. 23, 2021, as Appl. No. 17/408,849.
Application 17/408,849 is a continuation of application No. 16/736,741, filed on Jan. 7, 2020, granted, now 11,133,290.
Application 16/736,741 is a continuation of application No. PCT/CN2019/121821, filed on Nov. 29, 2019.
Prior Publication US 2021/0384166 A1, Dec. 9, 2021
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/5384 (2013.01); H01L 24/05 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a chip stack comprising:
multiple chips stacked together, each of the multiple chips comprising a bonding pad not covered by the multiple chips;
a molding layer encapsulating the multiple chips, wherein a first subset of the multiple chips is separated from a second subset of the multiple chips by the molding layer;
a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad; and
a redistribution layer above the molding layer and having:
a conductive layer coupled to the vertical conductive element; and
an insulating layer over and partially exposing the conductive layer.