US 11,688,693 B2
Semiconductor packages and method of manufacture
Wei-Yu Chen, Hsinchu (TW); Chun-Chih Chuang, Taichung (TW); Kuan-Lin Ho, Hsinchu (TW); Yu-Min Liang, Zhongli (TW); and Jiun Yi Wu, Zhongli (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 26, 2020, as Appl. No. 16/883,186.
Claims priority of provisional application 62/927,344, filed on Oct. 29, 2019.
Prior Publication US 2021/0125933 A1, Apr. 29, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/19106 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A package comprising:
an interposer structure free of any transistors, the interposer structure comprises:
an interconnect device;
a dielectric film surrounding the interconnect device;
first metallization pattern bonded to the interconnect device;
a second interconnect structure on an opposing side of the dielectric film as the first metallization pattern; and
a through via extending through the dielectric film, wherein the through via electrically connects the second interconnect structure to the first metallization pattern;
a first device die bonded to an opposing side of the first metallization pattern as the interconnect device;
a second device die bonded to a same side of the first metallization pattern as the first device die, wherein the interconnect device electrically connects the first device die to the second device die, wherein the interconnect device overlaps both the first device die and the second device die, and wherein the first metallization pattern comprises:
a first conductor extending continuously from a first connector of the first device die to a second connector of the interconnect device; and
a second conductor extending continuously from a third connector of the second device die to a fourth connector of the interconnect device; and
a core substrate bonded to an opposing side of the second interconnect structure as the dielectric film.