CPC H01L 23/481 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/31116 (2013.01); H01L 21/76283 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H01L 23/585 (2013.01); H01L 29/0649 (2013.01)] | 20 Claims |
1. A semiconductor structure, comprising:
a substrate that includes:
a handle layer,
an insulation layer arranged over the handle layer, and
a buried layer arranged over the insulation layer;
a polysilicon region extending downward through the buried layer and the insulation layer, and terminating in the handle layer; and
an etch stop layer located on the substrate;
at least one contact located on the etch stop layer;
at least one dielectric layer on the etch stop layer; and
a metal layer over the at least one dielectric layer.
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