US 11,688,626 B2
Nanosheet transistor with self-aligned dielectric pillar
Ruilong Xie, Niskayuna, NY (US); Kangguo Cheng, Schenectady, NY (US); and Julien Frougier, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 8, 2021, as Appl. No. 17/496,841.
Application 17/496,841 is a division of application No. 16/740,954, filed on Jan. 13, 2020, granted, now 11,195,746.
Prior Publication US 2022/0028729 A1, Jan. 27, 2022
Int. Cl. H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/22 (2006.01); H01L 21/3065 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/02532 (2013.01); H01L 21/22 (2013.01); H01L 21/3065 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/0665 (2013.01); H01L 29/16 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a nanosheet stack positioned over a substrate;
a dielectric pillar adjacent to the nanosheet stack, the dielectric pillar positioned on and in direct contact with a surface of a shallow trench isolation region of the substrate;
a source or drain (S/D) region on and in direct contact with the surface of the shallow trench isolation region such that a bottommost surface of the S/D region and a bottommost surface of the dielectric pillar are coplanar; and
a trench silicide on and in direct contact with a surface of the S/D region and on and in direct contact with a topmost surface of the dielectric pillar.