US 11,688,560 B2
Supporting-terminal-equipped capacitor chip
Shinobu Chikuma, Nagaokakyo (JP); and Tadateru Yamada, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Oct. 21, 2020, as Appl. No. 17/75,745.
Claims priority of application No. 2019-195046 (JP), filed on Oct. 28, 2019.
Prior Publication US 2021/0125785 A1, Apr. 29, 2021
Int. Cl. H01G 4/30 (2006.01); H01G 4/012 (2006.01); H01G 2/06 (2006.01); H01G 4/12 (2006.01); H01G 4/008 (2006.01); H01G 4/232 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 2/065 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/1218 (2013.01); H01G 4/232 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A supporting-terminal-equipped capacitor chip comprising:
a capacitor chip; and
a first supporting terminal and a second supporting terminal that hold the capacitor chip between the first supporting terminal and the second supporting terminal, the first supporting terminal and the second supporting terminal being electrically conductive; wherein
the capacitor chip includes:
a multilayer body including a plurality of dielectric layers and a plurality of inner electrode layers alternately layered along a layering direction, a first main surface and a second main surface facing each other in the layering direction, a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the layering direction, and a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to both the layering direction and the width direction;
a first outer electrode extending from the first end surface onto a portion of each of the first main surface and the second main surface adjacent to the first end surface; and
a second outer electrode extending from the second end surface onto a portion of each of the first main surface and the second main surface adjacent to the second end surface;
the plurality of inner electrode layers include a first inner electrode layer connected to the first outer electrode and a second inner electrode layer connected to the second outer electrode;
the first supporting terminal is connected to a first connection portion of the first outer electrode on the first main surface;
the second supporting terminal is connected to a second connection portion of the second outer electrode on the first main surface;
a portion of the capacitor chip other than the first connection portion and the first supporting terminal are separated from each other;
a portion of the capacitor chip other than the second connection portion and the second supporting terminal are separated from each other; and
the first connection portion and the second connection portion are located on the first main surface each at positions that place at least one side of the first and second connection portions to overlap the corresponding first or second end surface in the stacking direction without extending past the corresponding first or second end surface.