CPC G11C 29/50004 (2013.01) [G06F 11/073 (2013.01); G11C 29/50012 (2013.01); G11C 2029/5004 (2013.01)] | 20 Claims |
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of a plurality of write-to-read delay times for the memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of the plurality of write-to-read delay times, wherein the first set comprises different write-to-read delay times than the second set;
determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion; and
responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the range of the plurality of write-to-read delay times.
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