CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/20 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line (WL), a gate control line, and a bit line (BL);
wherein each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor; and
wherein the first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
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