US 11,688,471 B2
Short program verify recovery with reduced programming disturbance in a memory sub-system
Hong-Yan Chen, San Jose, CA (US); and Yingda Dong, Los Altos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 8, 2022, as Appl. No. 17/689,862.
Application 17/689,862 is a continuation of application No. 16/946,273, filed on Jun. 12, 2020, granted, now 11,282,582.
Prior Publication US 2022/0189565 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3436 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3413 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first voltage signal to be applied to a first plurality of word lines of a block of the memory array during a program verify recovery operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells formed around a channel in the block, the first plurality of word lines comprising a selected word line associated with a program operation and one or more data word lines adjacent to the selected word line on a source-side of the string of memory cells;
wherein the first voltage signal has a magnitude configured to create a channel potential difference between the first plurality of memory cells and one or more second memory cells coupled to one or more word lines adjacent to the selected word line on a drain-side of the string of memory cells.