US 11,688,467 B2
Defect detection in memories with time-varying bit error rate
Zhengang Chen, San Jose, CA (US); Sai Krishna Mylavarapu, Folsom, CA (US); Zhenlei Shen, Milpitas, CA (US); Tingjun Xie, Milpitas, CA (US); and Charles S. Kwong, Redwood City, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 14, 2021, as Appl. No. 17/347,570.
Application 17/347,570 is a continuation of application No. 16/215,267, filed on Dec. 10, 2018, granted, now 11,037,637.
Prior Publication US 2021/0304826 A1, Sep. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 16/26 (2006.01); G11C 29/42 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01)
CPC G11C 16/3404 (2013.01) [G06F 11/076 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/141 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G06F 2201/81 (2013.01); G11C 2029/0411 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to perform operations comprising:
determining that a bit error rate (BER) condition corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion;
determining a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component;
determining whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data; and
initiating a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.