CPC G11C 16/3404 (2013.01) [G06F 11/076 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/141 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G06F 2201/81 (2013.01); G11C 2029/0411 (2013.01)] | 20 Claims |
1. A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to perform operations comprising:
determining that a bit error rate (BER) condition corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion;
determining a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component;
determining whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data; and
initiating a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.
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