US 11,688,453 B2
Memory device, memory system and operating method
Taek Woon Kim, Seongnam-si (KR); and Jang Seok Choi, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 13, 2021, as Appl. No. 17/500,095.
Claims priority of application No. 10-2021-0014700 (KR), filed on Feb. 2, 2021.
Prior Publication US 2022/0246201 A1, Aug. 4, 2022
Int. Cl. G11C 11/406 (2006.01); G11C 29/44 (2006.01); G11C 11/4093 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/40622 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a bank memory array including memory cells;
a control unit configured to indicate a target row of the bank memory array in response to a refresh command received from an external source;
a refresh control circuit that provides a refresh row address in response to the control unit indicating the target row;
a row decoder that applies a refresh drive voltage to the refresh row address;
a status monitor that monitors row-specific status information for memory cells of the target row;
a status register that stores the status information under control of the status monitor; and
a data input/output (I/O) buffer that receives the status information from the status register and provides the status information to the external source in response to the refresh command.