US 11,688,452 B2
Refresh command control for host assist of row hammer mitigation
Bill Nale, Livermore, CA (US); and Christopher E. Cox, Placerville, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 3, 2022, as Appl. No. 17/686,287.
Application 17/157,826 is a division of application No. 16/370,578, filed on Mar. 29, 2019, granted, now 10,950,288, issued on Mar. 16, 2021.
Application 17/686,287 is a continuation of application No. 17/157,826, filed on Jan. 25, 2021, granted, now 11,282,561.
Prior Publication US 2022/0189532 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/406 (2006.01); G11C 11/4096 (2006.01); G06F 3/06 (2006.01)
CPC G11C 11/40611 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/4096 (2013.01); G11C 11/40618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device, comprising:
a memory array having multiple rows of memory including a target row;
a counter to track a number of activate commands received for the target row; and
input/output (I/O) hardware to receive an excess refresh command in response to receipt of a threshold number of activate commands for the target row, the excess refresh command to be in excess of a number of refresh commands necessary to refresh the multiple rows within a refresh window, the excess refresh command to indicate a refresh operation without indication of a row address for the refresh operation, wherein the DRAM device is to perform refresh of a victim row in response to the excess refresh command, the victim row subject to row disturb based on access to the target row, wherein the DRAM device is to determine the row address for the refresh operation.